FPGA Engineer at General Dynamics Mission Systems, Inc
Bloomington, MN
$98,759–$106,860from the description
Jul 13, 2026
Bloomington, MN
Jul 21, 2026
What this job asks for AI summary
This role centers on the design and development of ASICs and FPGAs for defense applications, covering the full development lifecycle from architecture definition and simulation through synthesis, place-and-route, timing analysis, and verification. It suits an early-career engineer with a relevant degree and some hands-on digital hardware design experience, and requires U.S. citizenship with eligibility for a DoD Secret clearance.
Junior level · 1+ years · National · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
Why we read it this way (6)
The posting does not specify a work location or CBSA — General Dynamics Mission Systems has facilities across multiple US states; the metro could not be determined from the text.
Clearance is stated as 'preferred at time of hire,' not a hard gate — however, US citizenship IS explicitly required due to the nature of the work. The clearance field is set to None (preferred only), but note that candidates must be eligible to obtain a DoD Secret clearance and must be US citizens.
The role covers ASIC and/or FPGA design — the JD treats these as interchangeable primary responsibilities, so both are captured as required with each listed as an alternative for the other.
SOC classification is a judgement call: ASIC/FPGA design is hardware-oriented digital design work, which sits closer to Electrical/Computer Engineering than pure software development. 15-1252 (Software Developers) is used as the closest available code given the design, simulation, and verification duties; 15-1299 (Computer Occupations, All Other) is noted as a plausible alternative.
The minimum experience requirement is 1 year (with a Bachelor's degree), or a Master's degree with no stated experience — this maps to a Junior-level role despite the relatively high salary band, which reflects the defense/cleared-work premium.
Ignored 3 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): ASIC design, RTL design, timing analysis.
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