FPGA Engineer II
CesiumAstro · Austin, TX
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Jun 30, 2026
Austin, TX
Jul 21, 2026
What this job asks for AI summary
This role centers on designing, verifying, and testing FPGA circuits for satellites, UAVs, launch vehicles, and other aerospace platforms. Day-to-day work spans HDL-level development covering high-speed serial interfaces, digital processing cores, and multi-clock designs, through to lab-based validation using instruments such as oscilloscopes and spectrum analyzers. It suits an engineer with at least two years of industry FPGA experience and a background in electrical or computer engineering.
Mid level · 2+ years · Austin, TX · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $137,069 (middle half $106,287–$172,440).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (8)
The role is titled 'FPGA Engineer II', which maps to a Mid-level band; the 2-year minimum experience requirement is consistent with that level.
SOC classification is Medium confidence: FPGA HDL engineering sits at the boundary between hardware/firmware design (15-1299, Computer Occupations All Other) and software development (15-1252). 15-1252 was chosen as the closest available code given the design, verification, and implementation nature of the work; 15-1299 is the runner-up.
The posting does not name a city, but CesiumAstro is headquartered in Austin, TX — that location is assumed here.
The posting references US export control regulations (ITAR) and requires the candidate to be a US person or eligible for authorization, but does not gate on a formal security clearance.
Lab instruments (oscilloscopes, spectrum analyzers, RF signal generators, vector signal analyzers) are listed together as a single required bullet; each has been extracted as a separate skill to reflect the distinct tools named.
Aerospace design/qualification, worst-case/FMECA/reliability analysis, and communications systems familiarity appear under 'Preferred Experience' and are not extracted as named tool skills — they are methodologies rather than concrete technologies.
No compensation figures are provided in the posting.
Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): FPGA design, PCB/board-level hardware design.
Read the full posting
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