CB Smart Recruit · Austin, TX

Salary
$260,000–$290,000
Posted
Jul 1, 2026
Location
Austin, TX
Last confirmed open
Jul 20, 2026

What this job asks for AI summary

A senior executive role heading the global backend engineering organization at a semiconductor company focused on HPC, automotive, and advanced SoC products. The position owns the full RTL-to-GDSII implementation flow across multiple concurrent SoC and MCU programs — covering synthesis, place and route, timing closure, and tape-out — while leading large, geographically distributed teams and driving methodology improvements. Suited to a seasoned semiconductor leader with 20+ years of physical design experience and a track record of advanced-node tape-outs.

Principal level · 20+ years · Austin-Round Rock-Georgetown, TX · Full-time

Pay in the description: $260,000–$290,000

Must have (10)
RTL-to-GDSIILogic synthesisFloorplanningPlace & RouteClock Tree SynthesisTiming closurePhysical verificationDesign signoffTape-outSoC integration
Nice to have (4)
EDA toolsHPCAutomotive semiconductorAI accelerators

We read this from the posting text with AI. Skim the description below before ruling yourself out.

Why we read it this way (9)

This is a Senior Director-level executive people-management role (large globally distributed org, direct reports, hiring, KPIs, organizational scaling), mapped to 11-3021. The alt code 15-1299 reflects the deep hands-on semiconductor/physical design technical expertise also required.

The title 'Senior Director' maps to Principal seniority given the org-wide scope, executive accountability across multiple global sites, and 20+ years required — well above the typical Senior band.

Degree requirement: a Master's in EE/CE is 'preferred'; a Bachelor's with extensive experience is explicitly accepted, so no hard degree gate is set.

The 30% target performance bonus and equity package are noted in the posting but cannot be represented in the compensation fields, which capture only the stated base salary range.

Foundry collaboration and EDA vendor experience are listed as 'highly desirable' in the preferred/experience section — treated as preferred.

HPC, automotive, AI accelerators, and networking silicon appear under 'Preferred Qualifications' — treated as preferred.

Physical implementation automation and backend methodology development appear in the required Technical Expertise section but name no specific tool or platform, so they are omitted from the skills list per extraction rules.

Visa sponsorship is explicitly unavailable; candidates must be US work-authorized.

Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): Advanced-node implementation, PPA optimization.

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