Senior Director, Physical Design & Backend Engineering (HPC) at Renesas Electronics
Austin, TX
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Jul 20, 2026
Austin, TX
Jul 23, 2026
What this job asks for AI summary
A senior leadership role responsible for the full RTL-to-GDS backend flow across multiple HPC SoC and MCU programs, from physical implementation and timing closure through tape-out signoff. The position oversees large, geographically distributed engineering teams, owns power, performance, and area targets, and drives standardization of tools, flows, and methodologies across sites. Suited to a seasoned semiconductor engineering leader with 20+ years of physical design experience.
Principal level · 20+ years · Full-time
We read this from the posting text with AI. Skim the description below before ruling yourself out.
Why we read it this way (7)
No work location or CBSA is specified in the posting; Renesas Electronics has major US offices (e.g., Santa Clara, CA) but the JD does not name a site — CBSA left blank.
This is a Senior Director role with direct leadership of large, multi-site global engineering teams, budget/delivery ownership across multiple SoC and MCU programs, and 20+ years required — clearly a top-of-ladder people-management role mapped to 11-3021.
The 'Senior Director' title carries Principal-level advertised seniority; the 20+ years requirement and org-wide scope also support Principal.
No specific EDA vendor tools (e.g., Synopsys, Cadence) are named by product; 'EDA tools' and 'DFT' appear only in cross-functional collaboration context and are marked preferred accordingly.
No compensation figures are provided; more information is noted to be shared during the hiring process.
The posting references U.S. export control regulations but does not gate candidates on holding a security clearance.
Ignored 3 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): SoC design, MCU design, advanced node implementation.
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