Castelion Corporation · Allen, TX

Salary
Posted
Jul 20, 2026
Location
Allen, TX
Last confirmed open
Jul 23, 2026

What this job asks for AI summary

This role centers on designing and building FPGA-based systems for a Hardware-in-the-Loop (HWIL) test environment used to validate defense hardware and algorithms before flight. The engineer will own FPGA architecture, development, and verification, integrating real-time 6-DOF simulation models with physical radar and sensor hardware. It suits experienced FPGA engineers comfortable working across electrical, software, and systems disciplines in an early-stage, ground-up build environment.

Senior level · 5+ years · Bachelor's required · Full-time

Must have (2)
VHDL, Verilog or SystemverilogXilinx/AMD FPGA
Nice to have (9)
HLSRTLFPGA simulationFPGA timing closureHWIL or Pilradar/RF systemshigh-speed interfacesoscilloscopeslogic analyzers

“or” means any one of them counts — you don't need all of them.

We read this from the posting text with AI. Skim the description below before ruling yourself out.

Why we read it this way (6)

No work location or city is stated in the posting; CBSA is left blank. The company (Castelion) appears to be a defense startup, likely US-based, but no specific office location is mentioned.

SOC classification is a judgement call: FPGA development sits at the boundary between hardware design (closer to electrical engineering) and software/firmware development. 15-1252 (Software Developers) is used because the role centers on writing and verifying HDL code and HLS-generated RTL — i.e., developing digital logic — rather than operating existing systems. 15-1299 (Computer Occupations, All Other) is the runner-up given the specialized embedded/hardware nature of the work.

VHDL, Verilog, and SystemVerilog are listed as interchangeable alternatives in the requirements ('VHDL, Verilog, or SystemVerilog'); VHDL is used as the primary name with the others in alternatives.

Security clearance: the JD states the role does NOT currently require a clearance but may in the future, and that the ability to obtain one is required. An active clearance is listed only as 'highly desired' under Preferred. This does not meet the hard-gate threshold, so the clearance requirement is set to None. U.S. citizenship IS a hard gate (explicitly required in Basic Qualifications).

HLS, RTL, simulation, timing closure, HWIL/PIL, radar/RF, high-speed interfaces, oscilloscopes, and logic analyzers all appear under the 'Preferred Skills and Experience' heading and are marked accordingly.

No compensation figures are provided in the posting.

Read the full posting

The employer publishes the full description on their own site — read it there ↗. Or sign in to read it here — it's free, and it also lets you track this application.

Apply

Apply on employer site ↗