Firmware Architect at TylSemi, Inc.
San Jose, CA
$150,000–$300,000
Jun 28, 2026
San Jose, CA
Jul 21, 2026
What this job asks for AI summary
A senior technical leadership role responsible for the full firmware and embedded software stack for PCIe/CXL chiplets — spanning on-die boot, link management, address translation, and power management through to host-side kernel drivers, virtualization shims, and IOMMU coordination. The position also covers team building, bring-up methodology, and direct engagement with compute-SoC and ATE customers. It suits a deeply experienced embedded firmware engineer with a strong background in high-speed interface silicon bring-up.
Senior level · 12+ years · Remote · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $175,140 (middle half $138,060–$220,730).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (8)
This role sits at the boundary between a hands-on Staff/Principal firmware architect and a people manager ('Team Building & Management', 'Set technical direction, roadmap, and clear subsystem ownership'). It is classified as a management role (11-3021) because explicit team-building and direction-setting responsibilities are listed; however, the dominant day-to-day work described is deeply hands-on firmware/embedded software engineering, making 15-1252 a strong runner-up.
The title carries no explicit seniority level word, so the title states no level. The 12+ years requirement and org-wide architecture ownership would normally suggest Staff or Principal, but at an early-stage startup this scope is typical for a senior individual contributor or first engineering hire — seniority is set to Senior per the tiebreaker rule.
Location is stated as 'Bay Area preferred' but the posting explicitly says the company hires the best people regardless of location, indicating remote is permitted.
The degree requirement is BS/MS in EE/CE/CS — the minimum stated is a Bachelor's degree.
Silicon bring-up experience of 5+ years is stated as a sub-requirement within the 12+ year overall experience gate; it is captured in the overall years minimum (12) rather than as a separate skill, as it is a role-level experience demand rather than a named technology.
ATE scripting (Teradyne UltraFLEX / Advantest T2000) and chiplet packaging concepts (EMIB, CoWoS) appear only under the 'Good To Have' section.
No compensation figures are provided in the posting.
This posting reads as a fully-remote role, so it was scored against the national candidate pool rather than a single metro.
Read the full posting
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