Senior Mixed-Signal Verification Engineer -Power Management ICs
TYLsemi, Inc. · San Jose, CA
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Jul 14, 2026
San Jose, CA
Jul 21, 2026
What this job asks for AI summary
This role centers on mixed-signal verification of high-current integrated voltage regulator (IVR) designs at a chiplet IP startup. Day-to-day work involves building analog behavioral models, running analog-digital co-simulations across PVT and Monte Carlo corners, and creating testbenches for power converter performance metrics such as transient response, loop stability, and protection sequences. It suits an experienced mixed-signal verification engineer with a background in power management ICs and familiarity with tools like Cadence Xcelium/Spectre or Synopsys VCS/CustomSim.
Senior level · 8+ years · Remote · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 75 people nationally plausibly meet what this posting asks for (software quality assurance analysts and testers). range 15–110
Applicant volume Light — Few people clear these requirements, so an application that does clear them gets looked at. Worth applying to even if you miss a nice-to-have.
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $106,594 (middle half $82,076–$136,109).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (9)
This is a highly specialized mixed-signal/analog verification role for power management ICs — it sits at the intersection of EDA tooling, hardware verification, and analog design. SOC 15-1253 (Software QA Analysts and Testers) is the closest standard code for a verification engineer writing testbenches and running regressions, but the role is heavily hardware/EDA-focused and does not map cleanly to any single BLS code; 15-1299 (Computer Occupations, All Other) is noted as a plausible alternative.
The JD states 'BSEE / MSEE with 8+ years relevant experience' — the 8-year figure is tied to the degree requirement pairing, making it the effective total experience floor. The earlier '5+ years of hands-on experience in mixed-signal verification' is a more specific sub-requirement; overall years minimum is set to 8 accordingly.
The degree requirement is BSEE or MSEE; since a Bachelor's is the minimum stated, the degree requirement is set to Bachelors.
Location is listed as 'Bay Area preferred' but the posting explicitly states remote-friendly hiring regardless of location, so remote is set to true.
Cadence Xcelium and Synopsys VCS are listed as interchangeable co-simulation front-ends; similarly, Spectre, FineSim, and CustomSim are listed as interchangeable analog solvers — captured accordingly.
SIMPLIS and PLECS appear together under the 'Nice to Have' section and are treated as interchangeable alternatives.
Python, Perl, and Tcl scripting appear under 'Nice to Have' and are treated as interchangeable alternatives for automation scripting.
No compensation figures are provided in the posting.
This posting reads as a fully-remote role, so it was scored against the national candidate pool rather than a single metro.
Read the full posting
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