Principal Engineer, AI Compiler at Renesas Electronics
San Jose, CA
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Jul 19, 2026
San Jose, CA
Jul 21, 2026
What this job asks for AI summary
This role centers on building and advancing AI compiler technology for next-generation automotive SoC hardware, specifically targeting neural processing units and multi-domain chips built on 3 nm silicon. Day-to-day work spans graph-level optimization, code generation, hardware-software co-design with SoC architects, and ensuring AI inference workloads meet automotive safety and real-time requirements. It suits a compiler engineer with deep experience in frameworks such as MLIR, LLVM, or TVM and a strong background in NPU or accelerator backends.
Staff level · National · Master's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $138,970 (middle half $107,524–$175,762).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
The job title is 'AI Compiler Engineer' with no explicit seniority level in the title itself; however, the posting internally describes two levels — 'Principal Engineer' and 'Sr Staff Engineer' — with slightly different Agile/communication expectations for each. The role is classified as Staff given the cross-team technical leadership scope (setting technical direction, mentoring senior engineers, influencing hardware architecture) without people-management responsibilities.
Degree requirement: the JD states 'MS/PhD (or equivalent experience)', which includes an explicit equivalent-experience escape hatch. However, the primary stated credential is MS/PhD; the degree requirement is set to Masters as the minimum formal degree named, noting that equivalent experience is accepted.
Location is not specified in the posting. No city, state, or remote designation is mentioned; cbsa fields are left blank and the US-based flag defaults to true given Renesas HPC team context and US export control language.
MLIR, LLVM, and TVM are listed together as interchangeable compiler IR/framework options ('MLIR, LLVM, TVM‑like systems, or proprietary compiler IRs'); MLIR is used as the primary name with LLVM and TVM as alternatives.
Automotive/safety-critical systems, heterogeneous SoC experience, and performance modeling appear under the explicit 'Nice to Have' section.
Ignored 6 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): AI compiler development, graph optimization, NPU/accelerator backend development, automotive/safety-critical systems, heterogeneous SoC architecture, performance modeling.
Read the full posting
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