Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING at GlobalFoundries
Santa Clara, CA
$167,000–$275,000from the description
Aug 9, 2026
Santa Clara, CA
Sep 24, 2026
What this job asks for AI summary
A Senior Manager / Deputy Director role at a global semiconductor foundry, responsible for leading a team of digital design engineers through the full lifecycle of processor core and SoC IP development — from microarchitecture definition and RTL implementation through tapeout. The position carries both deep technical ownership (PPA targets, synthesis, timing closure) and direct people-management responsibilities including hiring, mentoring, and performance management across potentially distributed teams.
Principal level · 12+ years · Bachelor's required · Full-time
Advertised as Senior, but the requirements read as Principal.
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $178,991 (middle half $141,096–$225,584). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 11, 2026. It is a model, not a headcount.
Why we read it this way (8)
The job location is not specified in the posting beyond GlobalFoundries' global footprint; no CBSA could be determined. The salary range suggests a US-based position.
This role is classified as a people-management position (11-3021) given explicit direct-report management, hiring, performance reviews, and succession planning duties. However, the role also carries substantial hands-on technical leadership (RTL review, architecture tradeoffs, design methodology), making 15-1252 a genuine runner-up.
Seniority is assessed as Principal: the role spans org-wide technical and people leadership at the Deputy Director level with 12+ years required, cross-functional executive stakeholder management, and responsibility for multiple teams and programs — well above a typical Senior individual contributor or single-team manager.
Advertised seniority is set to Senior based on the 'Senior Manager' framing in the title; 'Deputy Director' could imply a higher band but 'Senior' is the explicit level word used.
Verilog and SystemVerilog are listed together in the posting as a single parenthetical ('Verilog/SystemVerilog') but are distinct languages; both are emitted as separate required skills with each as an alternative for the other, reflecting that either satisfies the requirement.
'Advanced technology nodes' (7nm, 5nm, 3nm) is listed under Preferred Qualifications and is retained as a preferred skill, though it names a capability category rather than a specific named tool — included because it represents a concrete, assessable technical domain.
AI accelerators and multicore processors appear under Preferred Qualifications and are marked accordingly.
Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, timing analysis.
Read the full posting
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