Staff Engineer AI/ML at GlobalFoundries
Santa Clara, CA
$143,000–$275,000from the description
Aug 17, 2026
Santa Clara, CA
Sep 25, 2026
What this job asks for AI summary
This role at GlobalFoundries' MIPS team involves owning the RTL design and micro-architecture of a RISC-V vector CPU core and an AI-enabled matrix engine, covering the full design lifecycle from architectural exploration through detailed specification and implementation. The engineer will drive power, performance, and area goals, support functional verification, and collaborate with physical design and modeling teams. It suits a seasoned CPU hardware designer with deep microarchitecture expertise.
Senior level · 10+ years · Santa Clara, CA · Master's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 70 people in the Santa Clara, CA area plausibly meet what this posting asks for (software developers). range 40–100
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $217,796 (middle half $177,469–$231,052). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 20, 2026. It is a model, not a headcount.
Why we read it this way (6)
The SOC classification is a judgment call: this is a hardware RTL/microarchitecture role (CPU IP design), which is closer to hardware engineering than traditional software development. 15-1252 (Software Developers) is used as the best available fit within the permitted SOC list, since the role centers on writing and owning RTL (a form of design code); 15-1299 (Computer Occupations, All Other) is the runner-up.
The degree requirement is a hard gate stated as 'Master's with 10+ years OR PhD with 5+ years.' Master's is treated as the minimum qualifying degree; the overall years minimum is set to 10 (the lower bar paired with the lower degree). A PhD candidate with 5 years would also qualify, but the schema captures the minimum degree/experience combination.
Location is not explicitly stated in the posting. GlobalFoundries' MIPS team is historically based in Santa Clara, CA; this is an inference and should be verified.
SystemVerilog, Verilog, and VHDL are listed together in the required section with 'and/or' — they are treated as interchangeable alternatives on a single hard-gate requirement for HDL knowledge.
Skills such as 'microprocessor architecture,' 'vector processor design,' 'datapath design,' and 'logic simulation/waveform debugging' are domain competencies rather than named commercial tools, but they are explicitly called out as required knowledge areas in the qualifications section and are retained as concrete technical requirements for this hardware role.
Ignored 5 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, microprocessor architecture, vector processor design, datapath design, logic simulation / waveform debugging.
Read the full posting
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