AI/ML Software Engineer (2026 New College Graduate) at GlobalFoundries
Richardson, TX
$86,000–$148,000from the description
Aug 18, 2026
Richardson, TX
Sep 25, 2026
What this job asks for AI summary
This individual-contributor role at a semiconductor foundry focuses on characterizing AI/ML workloads, modeling hardware performance, and driving architecture decisions across SoC, memory, and compiler layers. The engineer will work at the intersection of hardware and software — analyzing compute/memory bottlenecks, contributing to open-source compiler infrastructure (MLIR, IREE), and translating findings into architectural recommendations for both engineering leadership and product stakeholders. Strong candidates will have hands-on experience with edge AI accelerators and AI compiler toolchains.
Senior level · Dallas-Fort Worth-Arlington, TX · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
Why we read it this way (7)
The posting lists three possible work locations — Dallas, Austin, and San Jose — with 100% in-office required. The CBSA is set to Dallas-Fort Worth as the first-named location; Austin (CBSA 12420) and San Jose/San Francisco Bay Area (CBSA 41940) are equally valid depending on where the candidate is placed.
A BS is the stated minimum degree, but an MS is explicitly preferred; because the JD accepts a BS (or 'equivalent'), the degree requirement is set to None rather than Bachelors.
The AI compiler infrastructure section (MLIR, IREE, TVM, TFLite) is framed with 'familiarity with … or equivalent' under Required Qualifications. MLIR is captured as the primary required skill with the others as alternatives, reflecting that the JD treats them as interchangeable. IREE, TVM, and TFLite are also listed separately as preferred given the posting's additional emphasis on each.
Vector/matrix CPU extensions (AVX/NEON/RVV, AMX/SME) and RISC-V appear only under Preferred Qualifications and are marked accordingly.
Model quantization and sparsity are described as 'a strong plus' within the Required section — they are captured as preferred rather than hard gates.
The role title carries no seniority level, but the scope (cross-functional architectural authority, presenting to senior leadership, individual contributor with org-wide influence) is consistent with a Senior engineer.
Ignored 4 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): AI/ML workload characterization, CPU architecture, SoC architecture, NPU / edge inference accelerators.
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