PMTS ASIC Digital Design IP ENGINEERING at GlobalFoundries
Santa Clara, CA
$167,000–$275,000from the description
Aug 9, 2026
Santa Clara, CA
Sep 24, 2026
What this job asks for AI summary
A Principal/Staff-level digital design engineering role at a semiconductor foundry, focused on microarchitecture development and RTL design for high-performance processor cores and SoC subsystems. The engineer will lead design initiatives across CPU pipelines, cache hierarchies, MMUs, and interconnects, while collaborating with verification, physical design, DFT, and firmware teams from concept through silicon bring-up. Suits a deep expert in processor microarchitecture with strong technical leadership experience.
Staff level · 12+ years · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
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How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $138,970 (middle half $107,524–$175,762). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 11, 2026. It is a model, not a headcount.
Why we read it this way (9)
No work location is specified in the posting; the CBSA and state fields are left blank. The salary range ($167K–$275K) suggests a US-based role, consistent with GlobalFoundries' US fab and design sites.
The title 'PMTS Digital Design Engineer' is a GlobalFoundries internal grade (Principal Member of Technical Staff), which maps to a Staff/Principal IC level. The scope — setting org-wide design guidelines, influencing multi-generation roadmaps, and mentoring both junior and senior engineers — supports a Staff-level classification rather than Senior.
SOC classification is Medium confidence: hardware RTL/microarchitecture design sits at the boundary between Software Developers (15-1252) and Computer Occupations, All Other (15-1299). BLS places digital logic/RTL designers most commonly under 15-1252 in practice, but 15-1299 is a reasonable alternative.
CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) are standard hardware design verification disciplines listed explicitly in the required qualifications.
RISC-V, ARM, MIPS, and ARC are listed together as interchangeable preferred CPU architecture experiences; they are captured as a single preferred skill with alternatives.
ISO 26262 and DO-254 are listed together as a preferred 'plus'; captured as a single preferred skill with the other as an alternative.
AI/ML acceleration, vector processing, multi-core/heterogeneous computing, and silicon bring-up experience appear only under Preferred Qualifications and are not captured as named tool skills — they describe domain experience rather than concrete named technologies.
Degree requirement: the JD states 'Bachelor's or master's degree' with no 'or equivalent experience' clause, so Bachelor's is treated as the minimum hard requirement.
Ignored 4 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, timing analysis, low-power design, performance modeling.
Read the full posting
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