Senior ASIC Physical Design Engineer, Cache Coherent Interconnects at NVIDIA Corporation
Santa Clara, CA
$136,000–$264,500from the description
Aug 9, 2026
Santa Clara, CA
Sep 24, 2026
What this job asks for AI summary
This role sits on NVIDIA's CPU Cache Coherent Interconnects Design Team and focuses on physical design of on-chip interconnect networks and last-level caches. Day-to-day work covers RTL synthesis, timing closure, floor-planning, and power/area optimization, with close collaboration with logic design teams on micro-architecture feasibility. It suits an experienced semiconductor physical design engineer with a background in high-frequency, high-performance chip design.
Senior level · 5+ years · Santa Clara, CA · Master's required · Full-time
We read this from the posting text with AI. Skim the description below before ruling yourself out.
Why we read it this way (7)
The role spans two leveled salary bands: Level 3 ($136,000–$218,500) and Level 4 ($168,000–$264,500); the pay band range shown covers both bands combined.
SOC classification is uncertain: VLSI/physical design engineering is not cleanly captured by any single SOC code in the allowed list. 15-1299 (Computer Occupations, All Other) is used as the closest fit; 15-1252 (Software Developers) is the runner-up given the RTL/synthesis work, though the primary work is hardware physical design rather than software.
The degree requirement is a Master's in EE, CE, or CS 'or equivalent experience.' Because the posting lists the degree first and frames it as the baseline, it is treated as the minimum formal requirement; however, the 'or equivalent experience' clause means some candidates without a Master's may still qualify.
Verilog, RTL design, DFT, and ECO are listed under a 'preferred' framing ('preferred as is a deep understanding of…') and are marked accordingly.
Interconnect/cache/core design experience is described as 'desirable' and is captured implicitly in the physical design skill; no separate named tool was specified for it.
Location is not explicitly stated in the posting; NVIDIA's CPU design teams are headquartered in Santa Clara, CA, which is used as the default CBSA.
Ignored 4 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): physical design, timing analysis, floor-planning, RTL design.
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