Principal AI Silicon Architect at Microsoft
Mountain View, CA
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Aug 3, 2026
Mountain View, CA
Sep 24, 2026
What this job asks for AI summary
A silicon architecture role focused on defining and developing AI accelerator chips — writing architecture specifications, building functional and analytical models of IP blocks, and guiding cross-functional teams (design, DV, firmware, emulation, kernel) through the full silicon development lifecycle. The ideal candidate brings deep experience leading multiple end-to-end silicon programs and expertise in ML acceleration, SoC/multi-chiplet design, and hardware/software co-design for high-performance computing.
Principal level · 10+ years
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $119,144 (middle half $81,115–$160,963).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 5, 2026. It is a model, not a headcount.
Why we read it this way (6)
The degree requirement is tiered: Doctorate + 7 years, Master's + 10 years, Bachelor's + 12 years, or equivalent experience — because equivalent experience is explicitly accepted, no minimum degree is flagged as a hard gate.
The posting requires export-control eligibility verification (citizenship or protected status documentation) as a condition of employment — this is not a US security clearance but is a notable hiring constraint.
The role title is not given; seniority is assessed as Principal based on the requirement to have led at least three end-to-end silicon programs, 10+ years of silicon architecture experience, and org-wide architectural direction-setting scope.
SOC 15-1299 (Computer Occupations, All Other) is used because silicon/chip architecture sits outside standard software developer or systems analyst categories; 15-1252 (Software Developers) is noted as a secondary possibility given the functional modeling and hardware/software co-design elements.
Domain expertise areas (ML acceleration, SIMD/SIMT, NoC, memory subsystem) are listed under a 'recognized expertise in one or more of the following' framing — they are preferred specializations rather than individual hard gates.
Ignored 5 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): silicon architecture, AI accelerator architecture, SIMD/SIMT vector processor architecture, multi-chiplet architecture, hardware/software co-design.
Read the full posting
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