Digital ASIC Design Engineer for Mixed-Signal IPs at Qualcomm
San Diego, CA
$115,600–$173,400from the description
Jul 1, 2026
San Diego, CA
Jul 21, 2026
What this job asks for AI summary
This role centers on the RTL and ASIC design of mixed-signal IP blocks — including DACs, ADCs, and PLLs — from micro-architecture definition through to physical implementation and post-silicon bring-up. The engineer works alongside analog, verification, and physical design teams to develop, validate, and integrate these IPs into larger SoCs, applying techniques in digital signal processing, low-power design, DFT, and formal verification. It suits engineers with a solid grounding in the full front-end ASIC flow and familiarity with mixed-signal design challenges.
Mid level · 3+ years · San Diego, CA · Master's required · Full-time
“or” means any one of them counts — you don't need all of them.
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Why we read it this way (7)
This is a hardware/ASIC engineering role (RTL, GDSII, DFT, STA, synthesis) — not a software development role in the traditional sense. No SOC code in the allowed list cleanly covers 'ASIC/RTL Design Engineer'; 15-1252 (Software Developers) is the closest available code, but the fit is imperfect. 15-1299 (Computer Occupations, All Other) is listed as the alt code for the same reason.
The 'Required for this Role' section states a Master's degree and 3+ years of RTL/ASIC experience. However, the 'Minimum Qualifications' section at the bottom accepts a Bachelor's + 2 years, Master's + 1 year, or a PhD alone. The Master's + 3 years gate from the 'Required for this Role' section is treated as the primary requirement since it is explicitly labeled as such; the degree requirement is set to Masters accordingly.
The location is not explicitly stated in the posting, but Qualcomm's Mixed-Signal IP team is headquartered in San Diego, CA — the CBSA is inferred from the company's known primary location.
Python and Perl appear only under Preferred Qualifications as automation/scripting tools; Python is listed as the primary with Perl as an alternative.
SerDes DDR PHY, PLLs, DACs, ADCs, and sensors experience (2+ years) is listed under Preferred Qualifications alongside the mixed-signal IP context.
Seniority is assessed as Mid: the minimum gate is 3 years (or as low as 1 year under minimum qualifications), and the role title carries no explicit level. The preferred profile (PhD + 5 years) would suggest Senior, but the hard gate supports Mid.
Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, ASIC design.
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