ASIC Intern – Digital/Mixed-Signal Design & Custom Hardware at Ludwig Computing
Mill Valley, CA
$41,600–$83,200
Jul 28, 2026
Mill Valley, CA
Jul 29, 2026
What this job asks for AI summary
An internship at an AI hardware startup focused on ASIC-level digital design, working alongside the founding team on RTL development, functional simulation, synthesis, and physical design readiness for custom compute blocks targeting AI workloads. Candidates should be pursuing a degree in Electrical Engineering or Computer Science, with hands-on RTL coding skills in Verilog or SystemVerilog and familiarity with ASIC design flows.
Junior level · Internship
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $138,970 (middle half $107,524–$175,762).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 29, 2026. It is a model, not a headcount.
Why we read it this way (5)
The SOC classification is uncertain: hardware RTL/ASIC design sits closer to Electrical/Computer Hardware Engineering (17-2061/17-2070, not in the allowed list) than to Software Developers (15-1252). 15-1252 is used as the closest available code because the role centers on writing RTL code and running EDA tool flows; 15-1299 (Computer Occupations, All Other) is flagged as the runner-up.
The degree requirement is listed as 'currently pursuing a degree in engineering' — this is an enrollment prerequisite for the internship, not a completed-degree hard gate, so the degree requirement is set to None.
Synopsys Design Compiler and Cadence Genus are presented as interchangeable examples ('e.g., Synopsys Design Compiler, Cadence Genus, or open-source equivalents') under the required qualifications; they are captured as a single skill with alternatives.
All 'Bonus if You Have' items (OpenCL, HLS, FPGA, numerical computing, hardware/software co-design, memory systems, analog/mixed-signal, PhD/MS status) are listed under an explicitly optional bonus section and are marked preferred.
Posting is for a internship engagement — the market benchmarks below price full-time roles, so read the comp comparison with that in mind.
Read the full posting
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