FPGA Engineer– Custom Compute Hardware at Ludwig Computing
Mill Valley, CA
$83,200–$166,400
Jul 28, 2026
Mill Valley, CA
Jul 29, 2026
What this job asks for AI summary
An internship at an early-stage AI hardware startup focused on FPGA-based prototyping of custom compute accelerators. The intern will design, implement, and verify RTL and HLS-based processing modules on FPGA platforms, build testbenches, run timing and area analysis, and support system integration. The role suits candidates with a digital design background who want hands-on exposure to hardware acceleration and ASIC-adjacent design flows.
Junior level · Bachelor's required · Internship
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $119,144 (middle half $81,115–$160,963).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 29, 2026. It is a model, not a headcount.
Why we read it this way (9)
No work location is specified in the posting; the CBSA and state fields are left blank. The role appears to be on-site given the collaborative, hands-on nature of the internship, but this is not stated explicitly.
SOC 15-1299 (Computer Occupations, All Other) is used because FPGA/hardware design engineering does not map cleanly to any single standard SOC code; 15-1252 (Software Developers) is the closest alternative given the RTL/HLS coding emphasis.
The degree requirement states 'B.S. degree or higher in engineering' as a hard requirement, so Bachelors is set as the minimum.
Verilog/SystemVerilog, VHDL, and C++ (for HLS) are listed together as interchangeable RTL/HLS options under the requirements section; they are captured as a grouped requirement with alternatives. HLS is also listed separately as a design methodology.
Vivado and Quartus are listed as interchangeable FPGA toolchain options under requirements.
'Digital logic fundamentals including pipelining and timing closure' and 'memory mapping and hierarchy on FPGA' are hard-gated requirements but name no specific tool or product, so they are captured under the broader 'digital logic design' and 'FPGA' skills rather than as separate generic concepts.
All 'Bonus if You Have' items are marked as preferred, as that section is explicitly framed as optional extras.
Ignored 5 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, digital logic design, hardware/software co-design, ASIC design, analog/mixed-signal design.
Posting is for a internship engagement — the market benchmarks below price full-time roles, so read the comp comparison with that in mind.
Read the full posting
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