Senior Principal ASIC FPGA Engineer at General Dynamics Mission Systems, Inc
Boise, ID
$191,146–$212,053from the description
Jul 21, 2026
Boise, ID
Jul 23, 2026
What this job asks for AI summary
A senior technical leadership role focused on the full ASIC design lifecycle — from architecture definition and RTL development through timing closure and tape-out. The position involves leading verification planning, conducting code reviews, mentoring engineers, and contributing to program scheduling and proposals. It suits an experienced RTL designer with a background in advanced-node ASIC tape-outs and the ability to work independently within a defense-oriented environment requiring a Secret clearance.
Senior level · 10+ years · Bachelor's required · Secret clearance · Full-time
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $138,970 (middle half $107,524–$175,762). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (10)
This role is ASIC/FPGA hardware design engineering — not software development in the traditional sense. No standard SOC code in the allowed list perfectly captures 'ASIC/Digital Hardware Design Engineer'; 15-1252 (Software Developers) is the closest available code because RTL design is a form of hardware description language coding and digital logic development, but the fit is imperfect. 15-1299 (Computer Occupations, All Other) is noted as an alternative for the same reason.
The job posting is tagged '#LI-Hybrid' but no specific work location or metro area is named. CBSA fields are left blank as a result.
The degree requirement is a Bachelor's in Electrical/Computer Engineering or related STEM field. A Master's degree is offered as an alternative with reduced experience (8 years vs. 10), so Bachelor's is the minimum hard gate.
Total experience minimum is 10 years (Bachelor's path); the Master's path requires 8 years. The lower bound of 10 years is used for the overall years minimum per the Bachelor's track, which is the minimum degree gate.
ASIC tape-out experience (including timing closure, physical verification, and post-silicon bring-up) is explicitly required in the 'What We're Looking For' section and treated as a hard gate, captured across the RTL, STA, and P&R skills.
FinFET process node experience (7nm, 5nm or similar) is described as 'a meaningful differentiator' — language that implies strong preference rather than a strict gate — so it is marked preferred.
Foundry flow experience (TSMC, GlobalFoundries, Samsung) is listed under required experience but framed with 'or equivalent', so alternatives are populated with the named peers.
Earned Value (EV) reporting and IMS contribution appear in the responsibilities section rather than a formal requirements block and are marked preferred accordingly.
Ignored 8 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, ASIC design, FPGA design, static timing analysis, clock domain crossing analysis, bus fabric design, power analysis, Earned Value reporting.
Requires a Secret clearance — the cleared population is a small fraction of this occupation, so the real candidate pool is materially smaller than the estimate below, which does not model clearance.
Read the full posting
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