Senior Verification Engineer - Scalable Coherency Fabric
NVIDIA Corporation · Santa Clara, CA
$136,000–$264,500from the description
Jun 30, 2026
Santa Clara, CA
Jul 21, 2026
What this job asks for AI summary
A senior verification engineering role focused on NVIDIA's scalable coherency fabric (SCF), a large-scale coherent interconnect used across its chip designs. Day-to-day work involves defining verification scope, building testbenches with SystemVerilog and UVM, applying formal verification techniques, and coordinating with architects and design teams. Suited to engineers with deep experience in coherent interconnect protocols such as ARM AMBA (AXI/ACE/CHI) and Network-on-Chip verification.
Senior level · 5+ years · Santa Clara, CA · Full-time
“or” means any one of them counts — you don't need all of them.
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How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $170,192 (middle half $126,400–$188,281). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
The posting covers two salary bands (Level 3: $136,000–$218,500; Level 4: $168,000–$264,500), so the offered range spans both levels. The comp fields reflect the full combined range.
Location is not explicitly stated; NVIDIA's CPU team is headquartered in Santa Clara, CA, which is used as the metro. The posting notes salary varies by location, implying possible multi-site hiring.
Degree requirement is None — the JD lists 'PhD, Master's, Bachelor's, or equivalent experience', explicitly accepting equivalent experience in lieu of a formal degree.
ARM AMBA protocols (AXI/ACE/CHI) are listed as a single requirement; AXI is used as the primary skill name with ACE and CHI as alternatives since the JD treats them as interchangeable options within the same protocol family.
Mentoring junior engineers is explicitly called 'a huge plus' and computer architecture is described as 'helpful' — both listed under the requirements section but with clearly optional language, so both are marked preferred.
The alt SOC (15-1252 Software Developers) is noted because hardware/RTL verification engineers sit at the boundary between QA/testing and engineering development; the primary classification as 15-1253 reflects the dominant verification/testbench focus.
Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): coherent interconnect architecture, computer architecture.
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