Austin, TX

Salary
$140,000–$175,000
Posted
Aug 11, 2026
Location
Austin, TX
Last confirmed open
Sep 24, 2026

What this job asks for AI summary

This is a hands-on senior ASIC design role at a quantum computing hardware company, focused on building a digital signal processing block from microarchitecture and RTL through silicon bring-up. The engineer will collaborate closely with physicists, optical engineers, and software teams to translate system requirements into production silicon, while also contributing to current FPGA designs. The role is hybrid in-office (Austin, TX or Boulder, CO) and suits someone with end-to-end ASIC design cycle experience and strong DSP expertise.

Senior level · 5+ years · Austin-Round Rock-Georgetown, TX · Master's required · Full-time

Pay in the description: $140,000–$175,000

Quick apply — this platform usually takes a CV and a few fields.

Must have (5)
RTLSystemVerilogDSPFPGACadence, Synopsys or Siemens Eda

“or” means any one of them counts — you don't need all of them.

We read this from the posting text with AI. Skim the description below before ruling yourself out.

How this req sits in the market our data

What gives you an edge
SystemVerilog2%DSP2%

Rare in this occupation — lead with these, and say what you built with them.

What the occupation pays Median $132,317 (middle half $83,374–$165,481). This posting is about at that midpoint.

Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 15, 2026. It is a model, not a headcount.

Why we read it this way (6)

The role lists two possible office locations — Austin, TX and Boulder, CO — with a hybrid requirement of at least 3 days per week in-office. The CBSA is set to Austin-Round Rock-Georgetown, TX as the first-named location; Boulder, CO (CBSA 14500) is an equally valid alternative.

The degree requirement is MS or PhD in Electrical Engineering or related field; MS is treated as the minimum hard gate.

'Cadence, Synopsys, or Siemens EDA' are listed as interchangeable EDA tool options — Cadence is named as the primary skill with the others captured as alternatives.

The posting sits most naturally in 15-1299 (Computer Occupations, All Other) because ASIC/hardware design does not map cleanly to any of the software-developer or systems-analyst SOC codes; 15-1252 (Software Developers) is noted as a runner-up given the RTL/digital design work.

Compensation includes an annual bonus and equity in addition to the stated base salary range, which cannot be represented in the structured fields.

Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): ASIC design.

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