Santa Clara, CA

Salary
$200,000–$350,000
Posted
Aug 18, 2026
Location
Santa Clara, CA
Last confirmed open
Sep 24, 2026

What this job asks for AI summary

A hardware design verification role focused on a custom, ground-up high-performance CPU within a Physical AI SoC. The engineer will own a functional domain end-to-end — from test planning and testbench development through coverage closure — covering units such as instruction fetch, decode, load/store, and caches. The role suits a seasoned verification engineer with deep CPU microarchitecture knowledge and hands-on UVM/SystemVerilog experience.

Senior level · 8+ years · Bachelor's required · Full-time

Quick apply — this platform usually takes a CV and a few fields.

Must have (4)
SystemVerilogUVMCC++
Nice to have (4)
ARM ISA or RISC-Vformal verificationgate-level simulationFPGA prototyping

“or” means any one of them counts — you don't need all of them.

We read this from the posting text with AI. Skim the description below before ruling yourself out.

How this req sits in the market our data

What gives you an edge
UVM1%SystemVerilog2%

Rare in this occupation — lead with these, and say what you built with them.

What the occupation pays Median $138,970 (middle half $107,524–$175,762).

Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 20, 2026. It is a model, not a headcount.

Why we read it this way (5)

SOC classification is a judgement call: design verification engineering sits at the intersection of hardware and software. 15-1252 (Software Developers) is the closest available code because the role primarily involves writing verification environments (testbenches, assertions, coverage, stimulus) in SystemVerilog/UVM/C++. 15-1299 (Computer Occupations, All Other) is the runner-up given the hardware-centric nature of the work.

ARM ISA and RISC-V are listed together under Preferred Qualifications as alternative knowledge areas; they are captured as separate preferred skills with each listed as an alternative for the other.

FPGA prototyping appears in the Responsibilities section as a support activity rather than a gated requirement, so it is marked preferred.

Formal verification and gate-level simulation appear only under Preferred Qualifications.

The degree requirement is a hard gate: 'BS or higher in Computer Engineering, Electrical Engineering or Computer Science' is stated under Required Qualifications.

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