Senior Firmware Development Engineer at Microsoft
Mountain View, CA
—
Aug 10, 2026
Mountain View, CA
Sep 24, 2026
What this job asks for AI summary
This role centers on building high-performance test applications and diagnostic/stress workloads for a custom AI hardware platform (MAIA), with emphasis on PCIe, memory subsystems, networking, and thermal/power characterization. The engineer will also develop profiling and benchmarking tools and end-to-end post-silicon validation tests, collaborating with AI frameworks, silicon validation, architecture, and firmware teams. It suits a seasoned systems software engineer with deep C++ and SoC validation experience.
Senior level · 5+ years · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $106,594 (middle half $82,076–$136,109).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 12, 2026. It is a model, not a headcount.
Why we read it this way (6)
The posting's education/experience matrix accepts equivalent experience in lieu of a degree, so no minimum degree is hard-gated.
The '7+ years in software development with C++' and '7+ years in post-silicon SoC or system validation' requirements appear under a block introduced by 'These requirements include, but are not limited to, the following specialized security screenings' — unusual framing, but the language is clearly gating; both are treated as hard requirements.
The overall years minimum is set to 5 (the lowest rung of the education/experience ladder: Bachelor's + 5 years), as equivalent experience is also accepted.
The hardware-interface skills (DMAs, PCIe, Memory, Network Controllers, Image decoders) are listed as 'experience with one or more of these,' making them individually preferred; PCIe and DDR/HBM are also central to the role description and are marked required accordingly.
SOC classification is Medium confidence: the role is primarily post-silicon test and validation (15-1253), but the volume of software development work (C++, profiling tools, end-to-end test frameworks) makes 15-1252 a plausible alternative.
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): post-silicon SoC validation.
Read the full posting
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