Senior Silicon Design Verification Engineer at Microsoft
Mountain View, CA
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Aug 16, 2026
Mountain View, CA
Sep 25, 2026
What this job asks for AI summary
This is a hardware verification and validation engineering role focused on pre-silicon SoC/subsystem verification and post-silicon bring-up. The engineer will develop C/C++ firmware-style tests, own FPGA prototyping platforms, write Python tooling, and conduct hands-on lab debug using JTAG, logic analyzers, and oscilloscopes. It suits an experienced engineer comfortable spanning RTL simulation, embedded firmware, and physical silicon bring-up.
Senior level · 5+ years · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $106,594 (middle half $82,076–$136,109).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 18, 2026. It is a model, not a headcount.
Why we read it this way (6)
The posting lists two overlapping experience tiers (one starting at 1/4/5 years and a second at 3/6/8 years by degree level), suggesting this may cover both a standard and a senior variant of the role. The minimum qualifying experience (Bachelor's + 5 years or equivalent) is used for the overall years minimum.
SOC classification is a genuine judgment call: the role spans pre-silicon verification/test development (15-1253) and embedded firmware/FPGA platform development (15-1252). The verification and test ownership framing is the primary signal, but a strong case exists for Software Developers given the firmware and RTL development scope.
The export-control clause requires proof of citizenship or protected US residency status as a condition of employment, but does not gate on a formal US government security clearance.
Degree requirement is set to None because the posting explicitly accepts 'equivalent experience' in lieu of any degree.
Protocol familiarity (AMBA, SPI, I2C/I3C, USB) and Makefile/assembly/linker scripts appear under a 'preferred/additional qualifications' framing ('Familiarity with…') and are marked preferred accordingly.
HAPS and Xilinx are named as example FPGA platforms ('such as HAPS or Xilinx') rather than hard requirements for a specific vendor; captured under the broader FPGA skill.
Read the full posting
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