Design Verification Engineer- AI Accelerator Lead at Velaura
Santa Clara, CA
$200,000–$350,000
Aug 18, 2026
Santa Clara, CA
Sep 25, 2026
What this job asks for AI summary
A hardware design verification role at a startup building custom AI inference SoCs, focused on verifying AI acceleration units — matrix and vector compute engines — from block-level RTL through full system bring-up. The engineer will own test planning, UVM environment development, reference model creation, and coverage closure for numerical compute hardware targeting LLM and vision workloads. Suits experienced DV engineers with a background in high-performance or AI accelerator verification.
Senior level · 8+ years · Bachelor's required · Full-time
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How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $106,594 (middle half $82,076–$136,109).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 20, 2026. It is a model, not a headcount.
Why we read it this way (4)
The posting lists 'BS or higher in Computer Engineering, Electrical Engineering or Computer Science' as a required qualification; the degree requirement is set to Bachelors accordingly.
Reference model experience (C, C++, or Python) is listed as required; Python is captured separately as preferred since the posting frames it as one of several acceptable options rather than a standalone gate.
PyTorch, ONNX, and compiler/runtime stack experience appear under Preferred Qualifications, as does formal verification and gate-level simulation — all marked preferred.
The alt SOC (15-1252 Software Developers) is noted because the role involves substantial environment and reference-model coding in C/C++/Python, blurring the line between DV engineering and software development; however, the primary function is verification/test, so 15-1253 is the primary code.
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