Principal Verification Engineer at Microsoft
Mountain View, CA
—
Aug 18, 2026
Mountain View, CA
Sep 25, 2026
What this job asks for AI summary
A pre-silicon design verification role focused on AI/ML chip components — CPUs, GPUs, SoCs, and custom IP/subsystems. The engineer will build and lead UVM-based testbenches, write constrained-random stimulus, scoreboards, checkers, and assertions, and collaborate closely with architecture and RTL design teams to validate correctness at both architectural and micro-architectural levels. Suits a seasoned verification engineer with deep ASIC/SoC experience.
Senior level · 8+ years · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $106,594 (middle half $82,076–$136,109).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 20, 2026. It is a model, not a headcount.
Why we read it this way (8)
The degree requirement accepts equivalent experience in lieu of any formal degree, so no minimum degree is flagged.
The posting lists three experience tiers tied to degree level (3+ years with Doctorate, 6+ with Master's, 8+ with Bachelor's); the overall years minimum is set to 8, the minimum for the most common path (Bachelor's), consistent with the separately stated '8+ years in ASIC/SoC verification' requirement.
The export-control citizenship/residency verification clause is a legal compliance condition, not a US security clearance gate; clearance is set to None.
UVM is listed in the main requirements block alongside 'C based test environments' as interchangeable options; both are captured under one skill entry.
Scripting languages (Zsh, Bash, Python, Perl) appear in the requirements section but are framed as 'experience in such as', suggesting any one suffices; Python is used as the primary name with the others as alternatives.
Interconnect fabrics, NoCs, and AXI-protocol-based IP experience is listed as 'demonstrated experience in one or more of the following' — treated as preferred rather than a hard gate on any single item.
AI/ML SoC experience is explicitly marked 'preferred' in the posting.
The role is hardware/pre-silicon design verification (not software QA in the traditional sense); 15-1253 is the closest available SOC code, with 15-1252 as a reasonable alternative given the significant testbench development and UVM coding involved.
Read the full posting
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