Senior Design Verification Engineer at Microsoft
Mountain View, CA
—
Aug 2, 2026
Mountain View, CA
Nov 9, 2026
What this job asks for AI summary
This is a pre-silicon hardware verification engineering role focused on building complex simulation and emulation environments for IP blocks, chips, and SoCs. The work involves writing verification components (scoreboards, sequences, assertions, coverage), developing test plans, triaging simulation failures, and collaborating with architects and design engineers. It suits engineers with deep experience in hardware verification methodologies and HDL/HVL toolchains.
Senior level · 5+ years · Bachelor's required
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $106,594 (middle half $82,076–$136,109).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 5, 2026. It is a model, not a headcount.
Why we read it this way (6)
The posting lists a tiered degree requirement (Bachelor's + 5 yrs, Master's + 4 yrs, Doctorate + 1 yr, or equivalent experience). Bachelor's is set as the minimum formal degree since equivalent experience is also accepted — however, the 'equivalent experience' path means a strict degree gate is debatable.
Total years minimum is set to 5 (the Bachelor's-path floor); the separate '6+ years of experience in creating simulation environments' requirement in the secondary qualifications block is a stronger signal but overlaps with the tiered gate.
The role involves export-controlled information; candidates must demonstrate US citizenship, permanent residency, refugee, or asylee status — this is not a security clearance but is a meaningful eligibility constraint not captured by the clearance field.
SOC classification is Medium confidence: the role is primarily hardware verification (pre-silicon test/QA), which maps best to 15-1253, but the depth of environment and tooling development also has characteristics of 15-1252 Software Developers.
Synthesizable RTL design experience is listed as a desired capability ('Design experience or ability to write synthesizable code') rather than a hard gate, so it is not emitted as a required skill.
Hardware emulation and FPGAs appear together as a single preferred item ('Experience with hardware emulation or FPGAs') and are captured as a preferred skill with an alternative.
Read the full posting
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