Senior Formal Verification Engineer at Velaura
Santa Clara, CA
$200,000–$500,000
Jul 24, 2026
Santa Clara, CA
Jul 27, 2026
What this job asks for AI summary
A senior-level role focused on leading formal verification for a next-generation Physical AI SoC, covering complex blocks such as CPUs, floating-point units, and vector/SIMD engines. Day-to-day work involves writing SVA properties, applying model checking and equivalence checking techniques, debugging counterexamples, and integrating formal proofs into the overall signoff flow. Suited to engineers with deep hands-on formal verification experience on complex digital hardware.
Senior level · 10+ years · Full-time
Pay in the description: $200,000–$500,000
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $138,970 (middle half $107,524–$175,762). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
No work location is specified in the posting. The compensation range ($200K–$500K/year) and the company's focus on Physical AI SoC suggest a US-based role, but remote eligibility is not stated; remote=false is a conservative default.
SOC classification is uncertain: formal verification of hardware (RTL/SoC) sits at the boundary of EDA/hardware engineering and software development. 15-1252 (Software Developers) is the closest available code given the heavy property-writing, scripting, and automation work; 15-1299 (Computer Occupations, All Other) is a reasonable alternative given the specialized hardware-verification nature of the role.
The $200K–$500K range is unusually wide; the posting notes that base pay depends on skills, qualifications, experience, and location, and that total compensation also includes performance incentives and equity — the figures likely represent base salary only.
JasperGold is listed as the primary tool with VC Formal, Questa Formal, and OneSpin as named alternatives in the same requirement ('JasperGold, VC Formal, or Questa Formal / OneSpin'); all four are captured under one skill entry.
C/C++/SystemC reference models vs. RTL appears only under Preferred Qualifications, so it is marked preferred. The primary named language captured is C++ with C and SystemC as alternatives.
Functional-safety standards (ISO 26262, IEC 61508, IEC 61511, ISO 13849) are listed together under Preferred Qualifications and are captured as a single preferred skill with alternatives.
Generic concepts such as 'assume-guarantee reasoning', 'abstraction', 'decomposition', 'computer architecture', 'microarchitecture', 'SoC design', 'cache coherence', 'memory consistency', 'CDC/RDC', and 'AI/ML hardware background' were not emitted as skills because they name no specific tool or technology.
Read the full posting
The employer publishes the full description on their own site — read it there ↗. Or sign in to read it here — it's free, and it also lets you track this application.